• Part: ST70135A
  • Description: ASCOTTM DMT TRANSCEIVER
  • Manufacturer: STMicroelectronics
  • Size: 198.95 KB
Download ST70135A Datasheet PDF
STMicroelectronics
ST70135A
ST70135A is ASCOTTM DMT TRANSCEIVER manufactured by STMicroelectronics.
ASCOTTM DMT TRANSCEIVER s DMT MODEM FOR CPE ADSL, PATIBLE WITH THE FOLLOWING STANDARDS: - ANSI T1.413 ISSUE 2 - ITU-T G.992.1 (G.DMT) - ITU-T G.992.2 (G.LITE) 1 & 2) OR BITSTREAM INTERFACE PQFP144 ORDERING NUMBER: ST70135A APPLICATIONS Routers at SOHO, stand-alone modems, PC modems GENERAL DESCRIPTION The ST70135A is the DMT modem and ATM framer of the STMicroelectronics ASCOT™ chipset. When coupled with ST70134 analog front-end and an external controller running dedicated firmware, the product fulfills ANSI T1.413 ”Issue 2” DMT ADSL specification. The chip supports UTOPIA level 1 and UTOPIA level 2 interface and a non ATM synchronous bit-stream interface. The ST70135A can be split up into two different sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections, with and without interleaving. The ST70135A is controlled and programmed by an external controller (ADSL Transceiver Controller, ATC) that sets the programmable coefficients. The firmware controls the initialization phase and carries out the consequent adaptation operations. s SUPPORTS EITHER ATM (UTOPIA LEVEL s 16 BIT MULTIPLEXED MICROPROCESSOR INTERFACE (LITTLE AND BIG ENDIAN PATIBILITY) s ANALOG FRONT END MANAGEMENT s DUAL LATENCY INTERLEAVED PATHS: FAST AND s ATM’S PHY LAYER: CELL PROCESSING (CELL DELINEATION, CELL INSERTION, HEC) s ADSL’S OVERHEAD MANAGEMENT s REED SOLOMON ENCODE/DECODE s TRELLIS ENCODE/DECODE (VITERBI) s DMT MAPPING/ DEMAPPING OVER 256 CARRIERS s FINE (2PPM) TIMING RECOVER USING ROTOR AND ADAPTATIVE FREQUENCY DOMAIN EQUALIZING s TIME DOMAIN EQUALIZATION s FRONT END DIGITAL FILTERS s 0.35µm HCMOS6 TECHNOLOGY s 144 PIN PQFP PACKAGE s POWER CONSUMPTION 1 WATT AT 3.3V April 2000 1/29 Figure 1 : Block...